TL;DR:
- XConn Technologies introduces revolutionary hybrid CXL 2.0 and PCIe Gen 5 switch.
- The XC50256 switch offers the lowest port-to-port latency and power consumption per port.
- Code-named “Apollo,” the switch is optimized for AI, ML, and HPC applications.
- Apollo supports CXL memory pooling and expansion with future-proof CXL 2.0 technology.
- Hybrid mode enables seamless coexistence of CXL and PCIe devices.
- XConn also releases PCIe Gen 5.0-only XC51256 switch, ideal for processing configurations.
- Apollo switch doubles switch lanes, halves port-to-port latency and power consumption.
- Industry leaders acknowledge XConn’s role in advancing CXL adoption.
- XConn’s leadership contributes actively to CXL Consortium, Open Compute Project, and PCI-SIG.
Main AI News:
In a move that sets a new benchmark for innovation in high-performance computing and AI applications, XConn Technologies (XConn) has proudly introduced an unprecedented solution—the world’s premier hybrid CXL 2.0 and PCIe Gen 5 switch. Fusing the prowess of Compute Express Link™ (CXL™) technology with the agility of Peripheral Component Interconnect Express® (PCIe®) Gen 5 interconnect technology within a singular 256-lane SoC, the XConn switch redefines industry standards. With the lowest port-to-port latency and power consumption per port, all encapsulated within a solitary chip, this cutting-edge technology ensures an unmatched total cost of ownership.
Debuting under the enigmatic code name “Apollo,” XConn Technologies celebrates the launch of the trailblazing XC50256 switch by emerging from its “stealth mode” at the distinguished Flash Memory Summit, hosted in Santa Clara, California, this week.
The Apollo switch’s conception stems from a ground-up approach, meticulously architected to cater to artificial intelligence (AI), machine learning (ML), and HPC applications. With the ability to actualize CXL memory pooling and expansion functions alongside existing CXL 1.1 hardware, the Apollo switch stands as a paragon of future-proofed design, seamlessly transitioning to accommodate the impending CXL 2.0 technology. Operating harmoniously in hybrid mode, this revolutionary switch accommodates both CXL and PCIe devices within the same system, providing an unparalleled level of flexibility. This innovative approach empowers system vendors to curate AI systems with a harmonious amalgamation of components, orchestrating a seamless transition from PCIe to CXL within a heterogeneous computing ecosystem.
Gerry Fan, the visionary CEO of XConn, elaborates, “Our record-breaking Apollo switch sets an unassailable standard in both flexibility and performance for the forthcoming generation of processors and memory. Apollo’s release underscores our resolute commitment to expediting AI computing across data centers and HPC applications. Representing the epitome of scalability, cost efficiency, and high-performance interconnect technology, Apollo is meticulously crafted to satisfy the stringent demands of both PCIe and CXL prerequisites, all encapsulated within a singular chip.” Fan further states that XConn’s dedication extends to collaborating with the industry at large to expedite CXL’s adoption and advance the realm of AI computing.
Expanding its spectrum of offerings, XConn also unveils the XC51256, a PCIe Gen 5.0-exclusive switch. Bolstered by 256 lanes, this product emerges as the densest PCIe Gen 5.0 switch, boasting nearly twice the lanes compared to its closest competitor. Tailored for Just-a-Bunch-Of-GPUs (JBOG) and Just-a-Bunch-Of-Accelerators (JBOA) processing configurations, the XC51256 stands as a testament to XConn’s commitment to efficient design. By rendering industry-low latency and power consumption while economizing precious board space, this solution liberates customers from the complexity of multiple chips, showcasing a single-chip marvel.
In the dynamic landscape of data-intensive workloads like AI/ML and genomics processing, connectivity emerges as the defining challenge. XConn’s Apollo obliterates the bandwidth barrier, nearly doubling the switch lanes delivered by its contemporaries, while also halving port-to-port latency and power consumption per port.
Jim Pappas, Director of Technology Initiatives at Intel Corporation, praises XConn’s role in the burgeoning CXL ecosystem: “XConn is an active participant in the expanding CXL adoption ecosystem. By bridging the design chasm between PCIe and CXL, XConn Technologies’ cutting-edge interconnect technologies drive the industry forward as CXL solidifies its stance as the premier standard for AI and HPC applications.”
Steve Pawlowski, Corporate Vice President of Advanced Memory Systems at Micron, echoes the sentiment, emphasizing CXL 2.0’s pivotal role in ushering in scalable memory capacity: “CXL 2.0 stands as the paramount emerging technology, enabling memory capacity well beyond traditional direct-attached approaches. XConn’s low-latency CXL switch propels the creation of expansive, sharable memory pools across multiple servers to cater to the escalating demands of AI and HPC workloads. Micron eagerly continues its partnership with XConn to usher in advanced CXL solutions that propel the CXL ecosystem to greater heights.”
Conclusion:
XConn Technologies’ introduction of the XC50256 hybrid switch signifies a transformative leap in high-performance computing. By seamlessly integrating CXL 2.0 and PCIe Gen 5 technologies, XConn addresses critical challenges in AI and HPC domains. The ability to pool and expand memory, alongside a flexible hybrid mode, positions XConn as a driving force in the industry. The XC50256’s launch, complemented by the XC51256’s density, paves the way for enhanced memory solutions and solidifies XConn’s leadership in advancing the CXL ecosystem. This monumental advancement holds the potential to reshape the landscape of high-performance computing and accelerates the trajectory of AI and HPC applications.
