TL;DR:
- Cadence introduces a portfolio of domain-specific apps enhancing its Palladium Z2 Enterprise Emulation System.
- These apps manage system design complexity, improve system-level accuracy, and accelerate low-power verification for advanced applications.
- Key apps include 4-State Emulation, Real Number Modeling, and Dynamic Power Analysis.
- Industry’s first 4-state emulation capability enables X-propagation acceleration for complex SoCs.
- Real number model emulation enhances mixed-signal simulation.
- Next-gen Dynamic Power Analysis app is up to 5X faster for power analysis.
- Emphasis on high performance, fast compilation, and efficient debugging.
- Integration within the Cadence Verification Suite supports Intelligent System Design™ strategy.
Main AI News:
In a strategic move to elevate the capabilities of its flagship Palladium Z2 Enterprise Emulation System, Cadence Design Systems, Inc. has introduced a groundbreaking portfolio of domain-specific applications. These cutting-edge apps are poised to revolutionize the management of the ever-increasing complexity in system design, enhancing system-level precision, and accelerating low-power verification for cutting-edge applications, including artificial intelligence and machine learning (AI/ML), hyperscale computing, and mobile technologies.
Today’s system designs continually push the boundaries of complexity, demanding increased capacity, performance, and streamlined debugging processes to meet stringent time-to-market requirements. Cadence’s latest offerings come to the forefront, with each of the new and enhanced Palladium Apps individually delivering industry-leading performance and features to confront these mounting challenges head-on. Here’s a glimpse into the innovative apps:
- 4-State Emulation App: A groundbreaking achievement, this app introduces the industry’s first 4-state emulation capability, unlocking the potential to accelerate simulations requiring X-propagation. This is particularly valuable for low-power verification of intricate System-on-Chips (SoCs) equipped with multiple switched power domains.
- Real Number Modeling App: Pioneering real number model emulation capability empowers the acceleration of simulations on mixed-signal designs, marking another industry-first achievement.
- Dynamic Power Analysis App: Redefining power analysis for multi-billion-gate, million-clock-cycle complex SoCs, this next-generation massively parallel architecture is up to 5 times faster than its predecessors.
Dhiraj Goswami, Corporate Vice President of Hardware System Verification R&D at Cadence, emphasized the importance of these advancements, stating, “To keep pace with the demanding requirements of today’s advanced SoC design landscape, customers require an emulation solution that offers exceptional performance with rapid, predictable compilation and debugging. With the introduction of these new Palladium Apps, we’re ushering in a transformative era in our industry, enabling our customers to accelerate X-propagation and mixed-signal simulations on emulation.”
The Palladium Z2 emulation system seamlessly integrates into the broader Cadence Verification Suite, aligning with the company’s overarching Intelligent System Design™ strategy, thus contributing to the pursuit of SoC design excellence.
Conclusion:
Cadence’s innovative Palladium Z2 and its suite of emulation apps signify a significant leap forward in the SoC verification landscape. These breakthroughs offer a solution to the escalating complexity of system designs and ensure faster, more precise verification, especially in critical areas such as low-power and mixed-signal simulations. This development will likely strengthen Cadence’s position in the market, attracting customers seeking high-performance emulation solutions for their advanced SoC designs.
