- Samsung achieves successful tapeout for high-performance mobile SoC design.
- Collaboration with Synopsys utilizing AI-driven EDA suite and IP on GAA process technologies.
- 300MHz performance increase demonstrated, along with 10% lower dynamic power.
- Utilization of Synopsys Fusion Compiler™ and DSO.ai for design optimization.
- High-performance core-specific techniques employed for enhanced results.
Main AI News:
Synopsys, Inc. revealed that Samsung Electronics has accomplished a successful production tapeout for its high-performance mobile System on Chip (SoC) design. Leveraging Synopsys.ai full stack AI-driven Electronic Design Automation (EDA) suite and a comprehensive array of Synopsys Intellectual Property (IP) on Samsung Foundry’s latest Gate-All-Around (GAA) process technologies, Samsung achieved a significant performance boost of 300MHz. This collaborative milestone highlights the synergy between Synopsys and Samsung in delivering outstanding Performance, Power, and Area (PPA) for their shared clientele, ushering in a new era of chips empowered with generative artificial intelligence (AI) capabilities on Samsung Foundry’s advanced process nodes.
“The enduring partnership between Synopsys and Samsung has consistently yielded cutting-edge SoC designs. Achieving the pinnacle of performance, power, and area for the most advanced mobile CPU cores and SoC designs in collaboration with Synopsys is truly remarkable,” stated Jongpil Lee, Vice President of SLSI at Samsung Electronics. “Not only have we showcased that AI-driven solutions can assist in meeting PPA targets for even the most advanced GAA process technologies, but through our collaboration, we have established an ultra-high-productivity design system that consistently delivers impressive outcomes.”
“The ever-increasing demand for superior PPA and energy efficiency in high-performance mobile chips necessitates high-performance core-specific EDA optimization across the entire stack,” remarked Shankar Krishnamoorthy, General Manager of the EDA Group at Synopsys. “Our comprehensive suite of PPA-enhancing capabilities tailored for CPUs and GPUs, integrated within the Synopsys AI-driven EDA suite and IP portfolio, empowers our shared clients to successfully craft chips with unparalleled quality-of-results for Samsung’s most advanced GAA processes.”
In order to meet Samsung’s rigorous performance and low-power demands for their mobile SoC design, Samsung utilized Synopsys’ acclaimed Synopsys.ai EDA suite. This encompassed leveraging Synopsys Fusion Compiler™ RTL-to-GDSII solution for superior PPA, coupled with Synopsys DSO.ai to further refine design targets and optimize quality of results. Employing high-performance core-specific methodologies including design partitioning optimization, multi-source clock tree synthesis (MSCTS), advanced wire optimization to mitigate crosstalk, and a virtual-flat hierarchical solution within the Synopsys Fusion Compiler solution, Samsung achieved a 300MHz performance increase compared to alternative methods. Remarkably, this was achieved alongside a 10% reduction in dynamic power consumption, while also saving Samsung weeks of manual design effort.
Conclusion:
The successful collaboration between Synopsys and Samsung, leveraging AI-driven EDA solutions, marks a significant advancement in the mobile SoC market. Achieving higher performance and lower power consumption not only showcases technological prowess but also sets a new standard for efficiency and quality in chip design. This collaboration demonstrates the importance of strategic partnerships and innovative methodologies in meeting the evolving demands of the semiconductor industry.
